Integrated circuit package and method

ABSTRACT

An integrated circuit package( 60 ) has a substrate ( 12 ) with a first surface ( 51 ) for mounting a semiconductor die ( 20 ) and a second surface ( 52 ) defining a via ( 70 ). A lead ( 26 ) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.

BACKGROUND OF THE INVENTION

[0001] The present invention relates in general to semiconductor devicesand, more particularly, to integrated circuits that include a grid arraypackage for housing a semiconductor die.

[0002] Integrated circuits that have high pin or lead counts often arehoused in grid array packages to achieve a small size. For example, ballgrid array (BGA) packages are used to provide chip scale or nearly chipscale integrated circuits that have between eighty and three hundredleads. A BGA package includes an interposer or substrate whose topsurface has a region for mounting a semiconductor die. Wire bondselectrically connect nodes of the semiconductor die to bonding padsformed on the top surface. Throughholes or vias through the substrateare used for connecting the bonding pads to access pads formed on thebottom surface of the substrate. The access pads typically are arrangedin a grid to minimize the area occupied by the integrated circuit'sleads. A solder mask is patterned with openings over each access pad toaccommodate small solder balls which are reflowed to function leads ofthe BGA package.

[0003] Current BGA packages suffer from a high cost due to the complexequipment needed to pick up the small solder balls, place them on theaccess pads and then to reflow the solder without disturbing the solderball positions. This equipment is expensive and occupies a large area ofa manufacturing facility. The cost is further increased because theaccess pads must be made large enough to ensure that the solder maskopenings do not overlap the boundaries of the access pads, therebyreducing the number of routing channels between access pads andincreasing the size of the substrate. A further problem is the presenceof lead in the solder balls, which is considered to be an environmentaland health hazard.

[0004] Hence, there is a need for an integrated circuit grid arraypackage and method which reduces the size and manufacturing cost of thepackage as well as the risk of environmental and health damage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1 is a cross-sectional view of an electrical system;

[0006]FIG. 2 is a top view of a first portion of an integrated circuit;

[0007]FIG. 3 is a bottom view of a second portion of the integratedcircuit;

[0008]FIG. 4 is a cross-sectional view of a portion of an integratedcircuit package after a first processing step;

[0009]FIG. 5 is a cross-sectional view of the portion of the integratedcircuit package after a second processing step; and

[0010]FIG. 6 is a cross-sectional view of the portion of the integratedcircuit package after a third processing step.

DETAILED DESCRIPTION OF THE DRAWINGS

[0011] In the figures, elements having the same reference numbers havesimilar functionality.

[0012]FIG. 1 is a cross-sectional view of an electrical system 10,including an integrated circuit 50 mounted to a motherboard 30.Integrated circuit 50 includes a semiconductor die 20 housed in anintegrated circuit package 60.

[0013] Motherboard 30 comprises a standard printed circuit boardconsisting of a base 32 formed with glass epoxy or other dielectricmaterial. Copper foil is laminated on a surface 33 of motherboard 30 andpatterned to provide attachment pads 34 for securing leads 26 of package60. Electrical and mechanical attachment of leads 26 is preferablyaccomplished with a lead-free solder which is reflowed after integratedcircuit 50 is positioned on motherboard 30. Alternatively, a conductivematerial may be selectively plated on motherboard 30 to attach leads 26.A standard solder masking material is applied to surface 33 andpatterned to form a solder mask 35 between attachment pads 34 to preventa system malfunction due to solder bridging.

[0014] Package 60 comprises an interposer or substrate 12 formed with adielectric material such as glass epoxy and/or bismaleimide-triazine(BT) resin. A copper foil formed to a typical thickness of abouttwenty-five micrometers is laminated on a first surface 51 of substrate12 and patterned to form a die attach flag 22 as well as a plurality ofbonding pads 16 and circuit interconnect traces 71. Die attach flag 22is used for mounting semiconductor die 20 to substrate 12 with athermally and/or electrically conductive epoxy or similar material.Bonding pads 16 are used for coupling electrical signals to die pads 14of semiconductor die 20 with wire bonds 18. In an alternate embodiment,semiconductor die 12 may be mounted to substrate 12 in a flip-chipfashion. The foil laminated on surface 51 is described as comprisingcopper, but a suitable alternative conductive material may be used whenappropriate. Package 60 includes a plastic molding compound 59 formed asshown to protect semiconductor die 20 from being damaged.

[0015] A copper foil formed to a thickness of about twenty-fivemicrometers is laminated on a surface 52 of substrate 12 and patternedto form a plurality of interconnect traces 72 and access pads 24.Integrated circuit 50 typically has between eighty and three hundredaccess pads 24 which are arrayed in a grid over surface 52 to minimizethe area of package 60. Copper is plated on access pads 24 to projectfrom surface 52 a typical distance of between fifty and one-hundredtwenty five micrometers to form leads 26. Although the foil and leads 26are described as comprising copper, another conductive material may beused in the alternative.

[0016] Openings are drilled in substrate 12 and copper plated to formvias 70 for coupling electrical signals between surface 51 and surface52. A standard solder masking material is applied to surface 52 andpatterned to form an insulating solder mask 27 as shown to providedamage protection and to prevent solder bridging when integrated circuit50 is attached to motherboard 30.

[0017] Note that leads 26 are mounted to motherboard 30 so as tomaintain a spacing 29 between surface 33 of motherboard 30 and surface52 of substrate 12. Spacing 29 allows leads 26 to flex to absorbdifferences in the thermal expansion characteristics between motherboard30 and integrated circuit 50. Such flexing improves the reliability ofintegrated circuit 50 by reducing the stress on semiconductor die 20.Flexing has an additional advantage of reducing shear stress where leads26 and attachment pads 34 come into contact, thereby avoiding a circuitfailure due to a detached lead. Similarly, flexing reduces the shearstress between leads 26 and access pads 24 to further improvereliability. As the length of leads 26 increases, the stress is reducedand reliability improves. Typically, leads 26 project from surface 52 adistance of between fifty and one hundred twenty-five micrometers toensure that integrated circuit 50 has a low cost while meeting specifiedreliability levels.

[0018]FIG. 2 is a top view of a first portion of integrated circuit 50,showing surface 51 of substrate 12 and semiconductor die 20 mounted ondie attach flag 22. Die pads 14 typically are formed around theperimeter of semiconductor die 20 and coupled to bonding pads 16 withwire bonds 18 as shown. Substrate 12 is drilled to form throughholes orvias 70 whose sidewalls are copper plated to a thickness of about tenmicrometers to provide electrical connections between surface 51 andsurface 52 of substrate 12. Note that bonding pads 16 are formed to havea typical center-to-center spacing of about two hundred micrometers tofacilitate wire bonding to die pads 14, which are formed with a typicalcenter-to-center spacing of about one hundred fifty micrometers. Thecopper foil on surface 51 is further patterned to form traces 71 toextend bonding pads 16 to vias 70.

[0019]FIG. 3 is a bottom view of a second portion of integrated circuit50, showing features formed on surface 52 in further detail. Vias 70 areextended through substrate 12 from surface 51. The copper foil laminatedon surface 52 is patterned to form traces 72 which extend to providesignal paths from vias 70 to access pads 24 as shown. Leads 26 areformed by plating copper onto access pads 24 as described below.

[0020]FIG. 4 is a cross-sectional view of a portion of integratedcircuit package 60 after a first processing step of the fabrication ofleads 26. Substrate 12, access pads 24, traces 72 and solder mask 27 areformed as described above. A photoresist layer 81 is applied to coversurface 52 of substrate 12 and patterned to form openings 82 to exposeaccess pads 24. Photoresist layer 81 is formed to a thickness determinedby the desired height of leads 26. In one embodiment, photoresist layer81 is formed to a thickness of about seventy five micrometers.

[0021]FIG. 5 is a cross-sectional view of the portion of integratedcircuit package 60 after a second processing step of the fabrication ofleads 26. Package 60 is placed in a plating apparatus (not shown) toplate copper onto access pads 24 to fill openings 82 with plated copper.Copper is plated outwardly from surface 52 in a direction indicated byarrow 85. The plating step typically is a timed process whose durationis determined by the thickness of photoresist layer 81. In oneembodiment, copper is electroplated in openings 82. In an alternativeembodiment, electroless plating is used to deposit copper in openings82. Although described as copper plating, a suitable alternateconductive material may be plated onto access pads 24.

[0022]FIG. 6 is a cross-sectional view of the portion of integratedcircuit package 60 after a third processing step of the fabrication ofleads 26. Photoresist layer 81 is removed using a standard removalprocess to leave leads 26 projecting outwardly from surface 52 as shown.In the described embodiment, leads 26 and access pads 24 are formed withthe same conductive material, i.e., copper, so a secure mechanicalinterface as well as a low resistance connection between leads 26 andaccess pads 24 is obtained. In addition, plating produces a grainstructure in leads 26 which results in a higher flexibility than wouldresult from a more crystalline structure. The higher flexibilityeffectively provides a greater strain relief when motherboard 30 andpackage 60 expand at different rates as the temperature varies, whichimproves reliability. Moreover, plating provides a high degree ofcontrol over the height of leads 26, which results in a more uniformspacing between motherboard 30 and integrated circuit 50 than isachieved by using solder balls to form package leads. This uniformityimproves reliability by ensuring that stress relief is more evenlydistributed among leads 26 than is provided using solder ball leads.

[0023] Although access pads 24 are formed with copper foil while leads26 are formed with plated copper, they have different structuralcharacteristics. Plated copper is formed with grains which typicallyhave a columnar structure whose grain boundaries run parallel to thedirection of plating.

[0024] That is the columnar grains of leads 25 run outwardly fromsurface 52 and parallel to the plating direction indicated by arrow 85of FIG. 5. Such a structure produces a high shear strength in leads 26.Moreover, a signal current I_(SIGNAL) flowing through one of the leads26 in the plating direction encounters fewer grain boundaries than acurrent flowing perpendicular to the plating direction. Therefore,I_(SIGNAL) flows through a lower electrical resistance.

[0025] Although solder mask 27 is shown as being formed beforephotoresist layer 81 is deposited and patterned, solder mask 27 mayalternatively be formed after leads 26 are plated 35 and photoresistlayer 81 is removed. In this embodiment, leads 26 are protected with ascreen template to avoid coating and a standard liquid solder maskingmaterial is flowed on surface 52 between leads 26. Such a process has anadvantage of avoiding the need to use photoresist process to form soldermask 27, thereby reducing the manufacturing cost of integrated circuit50.

[0026] In summary, the above described integrated circuit, package andmethod provide a higher reliability and lower cost than is achieved withprevious grid array packages and methods. A substrate has a firstsurface for mounting a semiconductor die and a second surface defining afirst via. A lead is formed with a conductive material to projectoutwardly from the second surface, where the conductive material extendsfrom the lead through the first via for coupling to the semiconductordie. The leads are formed with a plating process to improve theirflexibility and better control their height, which results in a highreliability. In addition, the use of copper leads has a furtheradvantage of a lower thermal resistance than packages using solder ballleads, which lowers the die temperature to further improve reliability.Moreover, the invention eliminates the need for lead-based or othertypes of solder balls to form the leads, thereby reducing the cost ofthe package and the risk of health or environmental damage.

What is claimed is:
 1. An integrated circuit package, comprising: asubstrate having a first surface for mounting a semiconductor die and asecond surface defining a via; and a lead formed with a conductivematerial to project outwardly from the second surface, where theconductive material is extended from the lead and through the via forcoupling to the semiconductor die.
 2. The integrated circuit package ofclaim 1, wherein the via is formed through the substrate to the firstsurface.
 3. The integrated circuit package of claim 2, wherein theconductive material extends along the first surface to form a pad forelectrically coupling to the semiconductor die.
 4. The integratedcircuit package of claim 1, wherein the conductive material is disposedalong the second surface from the via to the lead.
 5. The integratedcircuit package of claim 1, wherein the conductive material includescopper.
 6. The integrated circuit package of claim 5, wherein theconductive material includes plated copper.
 7. The integrated circuitpackage of claim 1, wherein the lead projects from the second surface adistance of at least fifty micrometers.
 8. The integrated circuitpackage of claim 1, wherein the substrate is formed with a dielectricmaterial.
 9. The integrated circuit of claim 8, wherein the dielectricmaterial includes bismaleimide-triazine resin.
 10. An integratedcircuit, comprising: a semiconductor die; a substrate having firstsurface for mounting the semiconductor die and a second surface defininga via; a signal path formed with a first material that is disposed alongthe first surface and through the via to route a signal between thesecond surface and the semiconductor die; and a lead formed with thefirst material for coupling to the signal path, where the lead projectsa distance from the second surface for receiving the signal.
 11. Theintegrated circuit of claim 10, wherein the substrate is formed with asecond material.
 12. The integrated circuit of claim 11, wherein thefirst material comprises a conductive material and the second materialcomprises an insulator.
 13. The integrated circuit of claim 10, whereinthe signal path extends along the first surface to form a pad, furthercomprising a bonding wire for coupling the signal from the pad to thesemiconductor die.
 14. The integrated circuit of claim 10, wherein thesignal path is routed along the second surface to form an access pad fordisposing the lead.
 15. The integrated circuit of claim 14, wherein theaccess pad is formed with a first thickness of the conductive materialand the lead is formed with a second thickness of the conductivematerial.
 16. The integrated circuit of claim 14, wherein the signalpath is extended along the second surface and the lead is projected froma surface of the access pad.
 17. A method of operating an integratedcircuit, comprising the steps of: providing a substrate having a firstsurface for mounting a semiconductor die and defining a via; applying asignal to a conductive material that is disposed to project from asecond surface of the substrate; and routing the signal along theconductive material and through the via to the first surface forcoupling to the semiconductor die.
 18. The method of claim 17, whereinthe step of routing includes the step of routing the signal throughplated copper toward the second surface.
 19. A method of making anintegrated circuit, comprising the step of plating a conductive materialto project outwardly from a first surface of a substrate to form a firstlead of the integrated circuit.
 20. The method of claim 19, furthercomprising the step of mounting a semiconductor die to a second surfaceof the substrate.
 21. The method of claim 20, further comprising thestep of forming a signal path on the second surface with the conductivematerial.
 22. The method of claim 21, further comprising the step ofdisposing the conductive material in a via defined by the substrate toextend the signal path from the second surface to the first surface ofthe substrate.
 23. The method of claim 22, further comprising the stepof disposing the conductive material on the first surface to extend thesignal path from the via to the first lead.
 24. The method of claim 23,wherein the step of disposing the conductive material on the firstsurface includes the step of forming an access pad on the first surface.25. The method of claim 23, further comprising the steps of: disposing aphotoresist layer on the first surface; patterning the photoresist layerto expose the access pads; and plating the conductive material on theaccess pads.
 26. The method of claim 25, wherein the step of patterningincludes the step of forming an opening in the photoresist layer overthe access pads.
 27. The method of claim 26, wherein the step of platingincludes the step of plating the conductive material within the opening.28. The method of claim 21, further comprising the step of wire bondingthe signal path to a node of the semiconductor die to couple a signalbetween the node and the first lead.
 29. The method of step 19, furthercomprising the step of forming a solder mask on the first surfacebetween the first lead and a second lead of the integrated circuit. 30.The method of claim 29, wherein the step of forming includes the step offorming the solder mask after the step of plating.
 31. The method ofclaim 19, wherein the step of plating includes the step of plating theconductive material in an outward direction for routing a currentthrough the first lead that flows parallel to the outward direction. 32.A method of forming an integrated circuit, comprising the steps of:providing a substrate having a first surface for mounting asemiconductor die; and plating a conductive material to extend outwardlyfrom a second surface of the substrate to form a lead of the integratedcircuit.
 33. The method of claim 32, wherein the step of platingincludes the step of disposing the conductive material to a height forattaching the lead to a mounting surface.
 34. The method of claim 33,wherein the step of disposing includes the step of disposing theconductive material to the height of at least fifty micrometers.
 35. Themethod of claim 33, wherein the step of disposing includes the step offorming the lead to a height that maintains a spacing between thesubstrate and the motherboard.
 36. A method of making an integratedcircuit, comprising the steps of: mounting a semiconductor die to afirst surface of a substrate; disposing a conductive material along thefirst surface and through a via of the substrate to form a signal pathof the integrated circuit between the first and a second surface of thesubstrate; and disposing the conductive material on the second surfaceto form a lead of the integrated circuit that is electrically coupled tothe signal path.
 37. The method of claim 36, wherein the step ofdisposing includes the step of plating the conductive material toproject outwardly from the second surface.